Design Verification WLAN - Sr Engineer
Core
Design verification engineer for next-generation SoCs focusing on WLAN (IEEE 802.11) IP and subsystem-level verification.
Role type
Senior IC digital design verification engineer
Builds
High-performance, low-power silicon solutions for wireless technologies
Domain
Semiconductor / Hardware Engineering / Wireless
Required skills
SystemVerilog, UVM/OVM, RTL verification, simulation and debugging, bus protocols (AMBA AXI/AHB/APB), power-aware verification (UPF/CPF), performance verification, gate-level and timing simulation, serial peripherals (UART/SDIO/SPI)
Preferred skills
CPU subsystem verification (ARM/RISCV), wireless protocol knowledge (IEEE 802.11), scripting (Perl/Tcl/Python), performance modeling, version control (Clearcase/Perforce)
Technologies
SystemVerilog, UVM, OVM, UPF, CPF, AMBA, ARM, RISCV, Perl, Tcl, Python, Clearcase, Perforce
Responsibilities
Develop and execute verification plans for complex SoC designs and IP blocks; Architect and implement testbenches using System Verilog and UVM/OVM methodologies; Perform RTL verification, simulation, and debugging; Collaborate with design, architecture, and software teams to ensure functional correctness; Contribute to IP design reviews and sign-off processes; Support post-silicon validation and bring-up activities; Analyze and verify interconnects, buses, and bridges for performance and protocol compliance; Conduct CPU subsystem verification including coherency, cache behavior, and interrupt handling; Perform power-aware verification using UPF/CPF and validate low-power design intent; Execute performance verification to ensure bandwidth, latency, and throughput targets are met; Perform Gate level and Timing Simulations to sign off on Timing closure; Analyze and verify serial peripherals like (UART/SDIO/SPI) and validate the Datapath integrity.
Seniority
Senior, hands-on IC
