FPGA Design Verification Intern
Core
Verifying Altera IPs such as PCIe, Ethernet, Search, and DR, including hardware debug/bring-up and regression triaging.
Role type
FPGA Design Verification Intern
Builds
High-Speed Protocol IP (PCIe, Ethernet, Search, DR)
Domain
Semiconductor / Hardware Verification
Required skills
Digital logic hardware design (System Verilog, Verilog, VHDL), Software programming/scripting (C/C++, Python), Regression triaging, Debugging
Preferred skills
FPGA development flows and tools (Quartus), Analytical problem-solving
Technologies
System Verilog, Verilog, VHDL, C, C++, Python, Quartus
Responsibilities
Verify Altera IPs (PCIe, Ethernet, Search, DR), Help in hardware debug/bring-up, Script DV development flow and automation, Support IP releases and rollout, Perform regression triaging and bug closures
Seniority
Intern
