DFT DV Engineer
Core
Develop test plans, scenarios, and coverage analysis for ASIC design verification and DFT implementation, ensuring debug logic works post-silicon for console APUs.
Role type
Senior IC DFT/Design Verification Engineer
Builds
SOC DFT definition, implementation, and verification for APUs
Domain
Semiconductor / ASIC Design
Required skills
ASIC design flow, SystemVerilog, C/C++, UVM, VCS, Shell/Perl/Python scripting, DFT (IEEE1149.1/6), Memory BIST, High-Speed IO (USB/PCIE/DDR/Display)
Preferred skills
Post-Si debug experience, ATE bring-up experience
Technologies
VCS, SystemVerilog, C, C++, UVM, Shell, Perl, Python, IEEE1149.1, IEEE1149.6
Responsibilities
Develop test plans according to specifications and review with Architect and Designer; Develop test scenarios to verify the design and analyze coverage; Complete verification tasks before Tape-Out; Participate in ATE bring-up and debug DFT patterns on ATE.
Seniority
Senior, hands-on IC
