DFT Engineer
Core
Define, implement, and verify Design for Test (DFT) features and architecture for System-on-Chip (SOC) microprocessors, ensuring testability and debug capabilities from specification to silicon bring-up.
Role type
Senior IC DFT Engineer (ASIC/SOC)
Builds
Testable SOC silicon with embedded DFT structures (SCAN, MBIST, etc.) and debug logic
Domain
Semiconductor / ASIC Design / Microprocessor
Required skills
ASIC DFT design and verification, full ASIC design flow knowledge, DFT architecture definition, DFT specification generation, implementation of SCAN/Boundary SCAN/MBIST/Analog Macro test logic, DFT verification, timing constraint generation, ATE bring-up and debugging, DFX logic design (debug, characterization, yield)
Preferred skills
Microprocessor design experience, strong problem-solving skills, fluent English communication
Technologies
SCAN, Boundary SCAN, MBIST, Analog Macro test logic, ATE, DFX tools
Responsibilities
Participate in SOC full Chip DFT feature and architecture definition; Responsible for DFT specification generation and review; Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic; Perform verification on all DFT structures; Generate DFT related timing constraints and work with PD team for timing closure; Generate and verify DFT structural patterns and functional patterns; Participate in ATE bring-up and debug the DFT patterns on ATE; Design and implement other DFX (debug, characterization, yield etc) logics
Seniority
Senior, hands-on IC
