DFT Engineer
Core
Design for Test (DFT) engineer for high-performance AI/ML chip architectures, responsible for RTL to tapeout implementation of test features.
Role type
Senior IC DFT Engineer
Builds
High-performance ASIC/SoC chips for AI/ML applications
Domain
Semiconductor / ASIC Design / AI Hardware
Deliverable
production ML models
Required skills
Verilog RTL, SystemVerilog, UVM, ATPG, MBIST, JTAG, Scan, Compression, Fault Models, Low-power design flows, Debug, Test coverage analysis
Preferred skills
Experience with Synopsys VCS/Verdi, ASST
Technologies
Synopsys VCS, Synopsys Verdi, Verilog, SystemVerilog, UVM
Responsibilities
Implement and integrate DFT features (scan, JTAG, compression, ASST, MBIST) into RTL from early design through tapeout. Own ATPG, test coverage analysis, and gate-level simulation. Plan, implement, and verify MBIST. Develop and refine DFx flows and methodology.
Seniority
Senior, hands-on IC
