ASIC Verification Engineer
Core
Design, implement, and maintain advanced verification infrastructure for ASIC products to ensure first-pass silicon success.
Role type
Senior IC ASIC verification engineer
Builds
ASIC IP blocks and complex digital subsystems
Domain
Semiconductor / ASIC Design
Required skills
SystemVerilog, UVM, constrained-random testing, SystemVerilog Assertions (SVA), C/C++, Python, Perl, Tcl, ARM architectures, AMBA protocols (AXI, AHB, APB), DSP algorithms
Preferred skills
Digital Signal Processing (DSP) algorithm translation, front-to-back ASIC design lifecycle expertise
Technologies
SystemVerilog, UVM, Python, Perl, Tcl, C/C++
