Staff Engineer Design System
Core
Develop high-performance SystemC/TLM2.0 models and QEMU-based virtual prototypes to accelerate SoC and system validation.
Role type
Staff Engineer, System Modeling & Virtual Prototyping
Builds
Virtual prototypes and SystemC/TLM2.0 models for SoC validation
Domain
Semiconductor / Embedded Systems / System-on-Chip (SoC)
Deliverable
production ML models
Required skills
C++, SystemC, TLM 2.0, UVM, RTL (System Verilog), Embedded C/C++, Embedded compilers (GNU, Tasking), Debuggers (PLS, Lauterbach T32), Machine Learning, Deep Learning
Preferred skills
Experience with ESL tools (Synopsys Virtualizer, ASTC, VLAB)
Technologies
SystemC, TLM2.0, QEMU, System Verilog, VisualStudio, g++, GNU, Tasking, PLS, Lauterbach T32, Synopsys Virtualizer, ASTC, VLAB
Responsibilities
Design and develop functional/cycle-accurate models using SystemC and ESL tools; Provide virtual prototype solutions for QEMU-based platforms; Perform requirements analysis and system architecture design; Verify models via unit testing, co-simulation with RTL, and SW-based system testing; Develop embedded system tests and debug using C/C++ and automated tools; Implement scalable and efficient AI systems.
Seniority
Staff, hands-on IC
