Senior Digital Design Verification Engineer - Hardware
Core
Verify design and implementation of cutting-edge SerDes IPs to enable gaming, AI, deep learning, and autonomous driving.
Role type
Senior IC digital design verification engineer (SerDes)
Builds
High-speed SerDes IPs consumed by standard and proprietary protocols
Domain
Hardware verification, high-speed serial interfaces, AI infrastructure
Deliverable
production ML models
Required skills
SystemVerilog, UVM, C/C++, hardware emulation, constrained-random stimulus, functional coverage, debugging
Preferred skills
Cadence Palladium, SerDes architectures, mixed-signal interfaces, high-speed protocols (PCIe, USB, SATA)
Responsibilities
Develop and execute verification plans for SerDes digital designs; bring up and debug verification environments on Cadence Palladium; write and maintain C/C++ reference models and test code; investigate failures across RTL and models; collaborate with architects and designers to close coverage.
Seniority
Senior, hands-on IC
