DFT Implementation Lead
Core
Lead the design, implementation, and validation of DFT IP and features for advanced packaging (2.5D/3DIC) and chiplet-based systems, ensuring high yield and quality for ATE and in-system testing.
Role type
Senior IC DFT Implementation Lead (Advanced Packaging/Chiplets)
Builds
Hierarchical DFT architectures, test wrappers, and validation flows for multi-die systems and licensable IP.
Domain
Semiconductor hardware design, advanced packaging, and chiplet ecosystems.
Required skills
Hardware DFT, JTAG protocols, scan and BIST architectures, memory BIST, boundary scan, ATPG, EDA tools (Tessent, TetraMax, Genus, Tempus, DC, PrimeTime), gate-level simulation, post-silicon validation, 2.5D/3DIC testing, TSV/micro-bump/hybrid-bond testing, IEEE 1838/1687/1500 standards, KGD screening, Tcl/Python/Perl scripting.
Preferred skills
Experience in startup environments, cross-functional collaboration with digital/analog/physical teams.
Technologies
Tcl, Python, Perl, Advantest, IEEE 1838, IEEE 1687, IEEE 1500, UCIe, BoW, 2.5D, 3DIC, TSV, micro-bump, hybrid-bond.
Responsibilities
Develop and implement DFT IP for ATE and in-system testing; define hierarchical DFT constraints and multi-mode sign-off; own DFT architecture for 2.5D/3DIC multi-die products; define KGD testing and screening strategies; architect DFT for die-to-die interfaces; deliver chiplet-level DFT collateral for customers.
Seniority
Senior, hands-on IC
