Principal Engineer Verification (f/m/div)
Core
Lead end-to-end verification of IPs and their integration, serving as the primary technical resource for the verification team.
Role type
Principal Engineer Verification (ASIC/SoC)
Builds
Verified IPs and integrated subsystems for chip products
Domain
Semiconductor / Hardware Verification
Required skills
SystemVerilog, UVM, constrained-random verification, formal verification, Python/Tcl/Bash/C/C++ scripting, Linux development, chip architecture knowledge, power-aware verification (UPF), AI agent development
Preferred skills
German language proficiency, RTL design experience, continuous integration flow expertise
Technologies
SystemVerilog, UVM, Python, Tcl, Bash, C, C++, Linux, UPF, AI agents
Responsibilities
Serve as the primary technical resource for the verification team; Lead and execute end-to-end verification of IPs and their integration; Lead and review third-party verification methodology; Actively guide and support the Chip Verification team; Define automation frameworks and reusability strategies; Act as a cross-site and cross-team bridge
Seniority
Principal, hands-on IC
