ASIC DFT Engineer I (Full Time) - United States
Core
Implement Hardware Design-for-Test (DFT) features to support ATE, in-system test, debug, and diagnostics for Cisco's core Switching, Routing, and Wireless products.
Role type
ASIC Design for Test Engineer
Builds
Hardware platforms for AI-era networking (Switching, Routing, Wireless)
Domain
Semiconductor / VLSI / Networking
Required skills
JTAG protocols, scan architectures, BIST (Built-In Self-Test), ATPG, EDA tools (TestMax, Tetramax, Tessent, PrimeTime), Python/Tcl/Perl scripting, gate-level simulation debugging (VCS)
Preferred skills
SystemVerilog, logic equivalency checking, test-timing validation, VLSI physical behaviors (electromigration, timing concepts), post-silicon validation
Technologies
SystemVerilog, VCS, TestMax, Tetramax, Tessent, PrimeTime, Python, Tcl, Perl
Responsibilities
Implement DFT features for ATE and diagnostics; Create and enhance automation scripts; Collaborate with Design, DV, and Physical Design teams; Validate test timing and logic equivalency using SystemVerilog; Utilize ATPG and EDA tools for pattern generation and analysis
Seniority
Entry-level (Bachelor's degree within 3 years or expected within 12 months)
