DFT Engineer
Core
Designing and implementing DFT solutions for SoC chips from specification through tape-out and silicon bring-up to ensure testability and yield.
Role type
Senior IC DFT Engineer
Builds
Production-ready ASIC chips with integrated DFT features
Domain
Semiconductor / ASIC Design
Required skills
DFT (Scan, MBIST, TAP, LBIST, IO, SerDes), ATPG, Verilog, Testbench generation, IEEE1149.1/6, IEEE1687, IJTAG, PDL, SSN, Test-STA, Analog/Digital circuit design, Device physics, Si processing, Logical/Physical synthesis
Preferred skills
DFT Compiler, Mentor TestKompress, TetraMax, Fastscan, Memory BIST (SRAM, CAM, eDRAM, ROM), Boundary scan
Technologies
TCL, PERL, RUBY, PYTHON, C++, Verilog, DFT Compiler, Mentor TestKompress, SSN, TetraMax, Fastscan
Responsibilities
Implementing DFT features including Scan, MBIST, TAP, LBIST, IO, and SerDes integration; Generating and verifying test vectors; Collaborating with STA and DI engineers for design closure; Debugging test vectors on ATE during silicon bring-up; Assisting with silicon failure analysis and yield improvement; Interfacing with customers and global engineering teams; Debugging customer returned parts.
Seniority
Senior, hands-on IC
