Senior Digital Verification Engineer
Core
Lead the development and execution of robust, reusable UVM verification environments for high-performance ASIC designs, ensuring functional coverage and first-silicon success.
Role type
Senior IC digital verification engineer (ASIC)
Builds
Scalable UVM test-bench architectures and verification components for complex digital IPs
Domain
Semiconductor / Electronic Design Automation (EDA)
Required skills
SystemVerilog, UVM, Cadence Xcelium, constrained-random verification, functional coverage, assertions (SVA), formal verification, root-cause analysis, mentoring
Preferred skills
Verification IP (VIP) development, low-power verification, Python/TCL/Makefile/Bash scripting, Git, CI/CD tools
Technologies
UVM, SystemVerilog, Cadence Xcelium, Python, TCL, Makefile, Bash, Git
Responsibilities
Define and implement scalable UVM test-bench architectures; Create and maintain reusable verification components (sequencers, drivers, monitors, scoreboards); Develop directed, random, and constrained-random test cases; Lead root-cause analysis of simulation failures and silicon bring-up bugs; Coordinate with design teams to close verification gaps before RTL freeze; Mentor junior verification engineers
Seniority
Senior, hands-on IC
