SMTS Silicon Design Engineer
Core
Perform DFT IP verification for complex CPU/ASIC projects from inception to tape-out, including test plan creation, scalable verification component development, and debugging.
Role type
Senior IC silicon design verification engineer
Builds
CPU/ASIC chips and DFT IP deliverables
Domain
Semiconductor / ASIC Design
Required skills
Design verification, Test bench architecture, Tool integration, Coverage analysis, Power domain management, Random constrained testing, Debugging regression failures, Post-silicon debug, Code coverage closure, Team leadership
Preferred skills
N/A
Technologies
UVM, SystemVerilog, Python, C++, Xcelium, Verdi, Questa, Synopsys VCS, Cadence Xcelium
Responsibilities
Create and develop IP-level test plans; Develop scalable verification components and random-constrained stimulus; Debug regression failures and perform post-silicon debug; Lead DV execution including project planning and quality checks; Provide technical support to SOC teams on DFT IP deliverables.
Seniority
Senior, hands-on IC
