SMTS Silicon Design Engineer
Core
Lead research group for emerging formal verification domains (security, safety, low-power) and steer technical roadmap for formalizing ISA and memory model for GFXIP design.
Role type
Senior IC silicon design engineer (formal verification)
Builds
Formal verification methodology and infrastructure for whole graphics design (datapath and control logic)
Domain
Semiconductor / Graphics IP / Formal Verification
Required skills
Formal verification of algorithms and engines, SystemVerilog Assertion, abstract model development, formal verification tools (JasperGold, VC Formal, Murphi), computer architecture, graphics pipeline, formal verification infrastructure development
Technologies
JasperGold, VC Formal, Murphi, theorem prover
Responsibilities
Define long-term strategy for formal verification expansion, develop cutting-edge formal verification methodology, scale formal verification to big and critical design, resolve challenging convergence issues, define and drive best-in-class formal verification infrastructure, lead definition/design/verification for ASIC development, determine architecture design and logic design
Seniority
Senior, hands-on IC
