DFT Engineer
Core
Design and implement Design for Test (DFT) strategies for ASIC SoC designs, covering test insertion, verification, pattern generation, and post-silicon debug to meet product test metrics.
Role type
Senior IC DFT Engineer
Builds
Production-ready ASIC chips with integrated testability and debug capabilities
Domain
Semiconductor / ASIC Design / Test Engineering
Required skills
DFT (Scan, MBIST, TAP, LBIST, IO, SerDes), ATPG, Verilog, Testbench generation, IEEE1149.1/6, IEEE1687, IJTAG, ICL, PDL, SSN, Test-STA, Analog/Digital circuit design, Device physics, Si processing, Logical/Physical synthesis, Transistor reliability
Preferred skills
Experience with DFT Compiler, Mentor TestKompress, SSN, TetraMax, Fastscan, SRAM/CAM/eDRAM/ROM BIST
Technologies
TCL, PERL, RUBY, PYTHON, C++, Verilog, IEEE1149.1, IEEE1149.6, IEEE1687, IJTAG, ICL, PDL, SSN, DFT Compiler, Mentor TestKompress, TetraMax, Fastscan
Responsibilities
Implement DFT features including Scan, MBIST, TAP, LBIST, IO, and SerDes integration; Generate and verify test vectors before tape-out; Collaborate with STA and DI engineers for design closure; Debug test vectors on ATE during silicon bring-up; Assist with silicon failure analysis and yield improvement; Interface with customers and global engineering teams; Debug customer returned parts on ATE
Seniority
Senior, hands-on IC
