DFT DV Engineer
Core
Develop test plans and scenarios for ASIC design verification, analyze coverage, and debug DFT patterns on ATE to ensure RTL quality for console APUs.
Role type
Senior IC design verification engineer (DFT)
Builds
SOC DFT definition, implementation, and verification for Strategic Silicon Solution Business Unit (S3BU) APUs
Domain
Semiconductor / ASIC Design / Hardware Verification
Required skills
ASIC design flow knowledge, SystemVerilog, C/C++, UVM, VCS simulation, test plan development, ATE bring-up, debug skills
Preferred skills
IEEE1149.1/6 (JTAG/BSCAN), Memory BIST, High-Speed IO (USB/PCIE/DDR/Display), post-Si debug, shell/Perl/Python scripting
Technologies
VCS, SystemVerilog, C, C++, UVM, ATE, JTAG, BSCAN
Responsibilities
Develop test plans according to specifications and review with Architect and Designer; Develop test scenarios to verify the design and analyze coverage; Complete verification tasks before tape-out; Participate in ATE bring-up and debug DFT patterns on ATE
Seniority
Senior, hands-on IC
