FY27 Intern - Design For Test for a Secure Asynchronous IP - 6 months, Montbonnot
Core
Improve test capabilities of a Secure Enclave IP (TESIC) for System-on-Chips, focusing on Memory Build-In Self-Test (MBIST), Design for Test (DFT), test coverage, and fault analysis within a security context.
Role type
Intern, Design for Test (DFT) Engineer
Builds
Robust and efficient test solutions for secure asynchronous IP
Domain
Semiconductor / Hardware Security / SoC
Required skills
Integrated Electronic Systems, Asynchronous Logic, Design for Test (DFT), Memory Build-In Self-Test (MBIST), Fault Analysis, Test Coverage, Hardware Design Flow, Security Context Adaptation
Preferred skills
Embedded Systems Security
Technologies
Well-known DFT and test tools
Responsibilities
Adapt standard DFT tools to security contexts and asynchronous logic features, improve MBIST capabilities, analyze test coverage and faults, learn global design flows and security principles
Seniority
Intern
