Principal Design Verification Engineer (AI Fabric Switches)
Core
Functional verification of complex ASICs for rack-scale AI infrastructure, focusing on connectivity solutions like CXL, Ethernet, NVLink, and PCIe.
Role type
Principal Design Verification Engineer (ASIC/SoC)
Builds
Functional verification of custom connectivity solutions and standards-based portfolio components.
Domain
Semiconductor hardware design, AI infrastructure, high-speed interconnects
Required skills
System Verilog, UVM, C++, C, Python, directed testing, constrained random testing, coverage closure, bug hunting, test plan development, emulation platform execution
Preferred skills
Formal methods, Perl scripting, Verification IPs for PCI-Express, Ethernet, InfiniBand, DDR4/5, NVMe, USB
Technologies
System Verilog, UVM, C++, C, Python, Perl, CXL, Ethernet, NVLink, PCIe, UALink, emulation platforms
Responsibilities
Develop full lifecycle verification plans and test sequences; execute tests in emulation platforms; debug failures collaboratively with RTL designers; identify and write coverage measures for corner cases; close coverage to ensure high-quality tape-out; automate verification infrastructure using scripting tools.
Seniority
Principal, hands-on IC
