DFT Engineer
Core
Design and implement DFT solutions for ASIC SoCs from specification through tape-out, ensuring testability and yield.
Role type
Senior IC DFT Engineer
Builds
ASIC chips with integrated DFT features (Scan, MBIST, TAP, LBIST, IO, SerDes)
Domain
Semiconductor / ASIC Design
Required skills
DFT (Scan, MBIST, ATPG, BIST), Verilog, Test Vector Generation, Silicon Debug, Yield Improvement, IEEE1149.1/6, IEEE1687, IJTAG, PDL, SSN, Test-STA
Preferred skills
Analog DFT, Device Physics, Si Processing, Logical/Physical Synthesis, Transistor Reliability
Technologies
DFT Compiler, Mentor TestKompress, SSN, TetraMax, Fastscan, ATE
Responsibilities
Implement DFT features (Scan, MBIST, TAP, LBIST, IO, SerDes); Generate and verify test vectors; Debug silicon failures and improve yield; Collaborate with Physical Design and STA teams; Interface with global customers and manufacturing teams.
Seniority
Senior, hands-on IC
