Emulation Verification Engineer (Japan Design Center)
Core
Utilizing emulation for verification of large Display and Wireless SoCs, including porting designs to the Palladium platform and executing test plans.
Role type
Emulation Verification Engineer
Builds
Verified chip designs for Display and Wireless SoCs
Domain
Semiconductor / Chip Design
Required skills
SystemVerilog, Verilog, UVM, Test bench creation, Regression management, Triaging, Palladium platform, Mixed signal modeling, Cross-functional collaboration
Preferred skills
Emulation bring-up and debugging, RTL to Emulation tool flow, FPGA flow (Xilinx/Altera), Silicon Validation, Synthesizable code, SystemVerilog assertions, C/C++ DPI, Scripting (Perl/Python/TCL), Low Power methodologies (UPF), UVM Acceleration
Technologies
Palladium, Veloce, Zebu, Xilinx, Altera, Verilog, SystemVerilog, UVM, C++, Perl, Python, TCL, UPF
Responsibilities
Porting designs onto the Palladium platform, Developing and utilizing monitors and checkers, Preparing and executing test plans, Collaborating with Design, Architecture, Power, Silicon Validation, Performance, and SW teams
Seniority
Mid-level, hands-on IC
