ASIC DFT Engineer
Core
ASIC DFT Engineer responsible for SoC DFT implementation, verification, debug, and post-silicon bring-up activities.
Role type
Senior IC ASIC DFT Engineer
Builds
Testable SoC designs with integrated DFT solutions for Broadcom APD
Domain
Semiconductor / ASIC Design / Digital & Analog DFT
Required skills
Scan insertion and compression, ATPG vector generation, Logic BIST design, Memory BIST insertion, Verilog coding, ATE debugging, Silicon failure analysis, Yield improvement, Cross-functional collaboration, TCL/Perl/Python/C++/Verilog scripting
Preferred skills
Analog DFT, IO DFT, SerDes DFT, 3nm node experience, Mentor TestKompress, TetraMax/Fastscan tools
Technologies
Verilog, TCL, Perl, Python, C++, TetraMax, Fastscan, Mentor TestKompress, ATE
Responsibilities
Define DFT specifications for ASIC, Implement Scan/MBIST/TAP/LBIST/IO/SerDes DFT, Collaborate with STA/DI engineers for design closure, Generate and debug test vectors pre-tape-out, Validate and debug test vectors on ATE during silicon bring-up, Assist with silicon failure analysis and yield improvement, Interface with global customer and manufacturing teams, Debug customer returned parts on ATE, Innovate DFT solutions for 3nm+ nodes, Automate DFT and test vector generation flows
Seniority
Senior, hands-on IC
