ASIC Physical Design
2,687 open positions
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Staff/Senior Staff Physical Design Floorplan & PDN Lead Enchargeai36India 8mo Architecting chip-level floorplans and Power Delivery Networks (PDN) for complex, large-scale SoCs to balance performance, power, and area.
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Sr Engineer, Design Enablement Renesas-ElectronicsHyderabad, in 8mo Develop and define Synthesis & Static Timing Analysis (STA) flows and methodologies for Advanced SoCs and MCUs on low geometry nodes (3/5/16/22nm).
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<Data Center>High-Speed Digital IC Design & Integration Engineer MediaTekHsinChu 8mo High-speed digital IC design implementation and integration from RTL to gate level.
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Senior FPGA Engineer (w/m/d) TrumpfRemote 8mo Designing digital hardware solutions and FPGA architectures for device platforms, from concept to implementation, ensuring optimal integration with RF and power electronics.
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Static Timing Analysis Engineer AccentureBengaluru 8mo Analyze and verify the timing of digital circuits to ensure they meet performance requirements under various operating conditions.
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IP RTL Design Engineer Samsung ElectronicsSSIR, Goldstone, Bangalore, India 8mo Senior IP Design Engineer developing RTL, synthesis, and verification for complex Image Sensor IP modules.
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2026 Intern-Physical Design Engineer QualcommShanghai, China 8mo Handle physical design tasks from Verilog netlist to GDS, including floorplanning, placement, CTS, routing, timing analysis, and signoff.
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DSP Firmware Engineer MarvellCordoba, Argentina 8mo Design, simulate, implement, and validate DSP ASICs for coherent optical transmission in fiber networks.
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Digital Design Manager Texas InstrumentsBengaluru, Karnataka, India 8mo End-to-end delivery of the first T28 industrial ASIC, combining full chip ownership with RTL team leadership to ensure first-time-right silicon and scalable architecture.
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Front-End CAD Methodology Engineer – Design/DV Interface AppleSan Francisco Bay Area, United States of America 8mo Design and manufacture next-generation, high-performance, power-efficient processor and system-on-chip (SoC) by creating robust, scalable methodology solutions for RTL Design and DV teams.
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Principal GPU Memory Architect NVIDIAUS, CA, Santa Clara $272k8mo Designing high-performance GPU memory systems and processor architectures to maximize power-constrained performance (perf/W, perf/mm, perf/$) and energy efficiency.
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FPGA Design Engineer ThermoteknixCambridge (UK) / Remote 8mo Design and contribute FPGA modules to a reusable library for thermal imaging, night vision, and augmented reality systems.
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Design Engineer BroadcomUSA-Colorado-Fort Collins-4380 Ziegler Road $60k8mo Physical implementation of high-performance custom CMOS ASICs for AI, Cellular, Networking, Computing, and Storage products.
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Firmware Development Engineer AlteraJerusalem, Israel 8mo Develop firmware for multi-protocol high-speed SERDES (up to 256Gbps) governing DSP and analog blocks, ensuring seamless interface management with higher-level system layers.
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Sr Principal Design Engineer CadencePUNE 04, IN 8mo Owns full DFT lifecycle for high-speed, low-power chip designs, defining test architecture and implementing RTL changes to ensure testability and timing closure.
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Sr Principal Digital Design Engineer ON SemiconductorBangalore, Karnataka, India 9mo Sr. Principal Digital Design Engineer developing Power Management ICs (LED drivers, SiC drivers, smart-Switches, efuses) for consumer, industrial, and automotive applications.
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SENIOR ASIC Engineer MicronHsinchu County, Hsinchu County, Taiwan 9mo Lead top-level SoC integration, RTL design, and high-speed protocol implementation (PCIe, USB, SATA) for memory and storage solutions.
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Emulation Hardware Project Manager Siemens-EdaRemote $130k9mo Planning, coordinating, and delivering emulation hardware support projects across engineering, IT, facilities, and vendor teams to ensure emulation platforms are deployed, maintained, upgraded, and supported on schedule.
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