SENIOR ASIC Engineer
Core
Lead top-level SoC integration, RTL design, and high-speed protocol implementation (PCIe, USB, SATA) for memory and storage solutions.
Role type
Senior IC ASIC Engineer (SoC & High-Speed Interface)
Builds
System-on-Chip (SoC) designs integrating CPU subsystems, interconnects, and high-speed I/O for DRAM/NAND storage products.
Domain
Semiconductor / Memory and Storage / SoC Design (via careerplan.io/jobs/39891348-senior-asic-engineer-at-micron)
Required skills
SoC RTL integration, CPU core integration (ARM/ARC/RISC-V), high-speed protocol design (PCIe/USB/SATA/DP/HDMI), SerDes/PHY design, Verilog/SystemVerilog, AMBA AXI/AHB, PPA optimization, DFT integration, pre-silicon validation, root-cause analysis.
Preferred skills
NVMe/CXL/DDR protocol knowledge, AI/ML concepts in engineering, EDA tool AI features, TCL/PERL/Python.
Technologies
VCS, VC-Spyglass, LINT, RDC, LEC, Design Compiler, Formality, PrimeTime, ARM, ARC, RISC-V, PCIe, USB, SATA, DisplayPort, HDMI, NVMe, CXL, DDR, AMBA AXI, AMBA AHB.
Responsibilities
Lead top-level SoC integration including CPU subsystems, interconnects, and test structures; Own SoC RTL integration, lint/CDC/RC checking, and timing closure; Integrate and validate CPU cores or clusters; Optimize PPA at CPU and SoC boundaries; Collaborate with DFT teams for scan and MBIST integration; Support pre-silicon simulation, emulation, and post-silicon bring-up; Drive root-cause analysis for silicon debug.
Seniority
Senior, hands-on IC
