2026 Intern-Physical Design Engineer
Core
Handle physical design tasks from Verilog netlist to GDS, including floorplanning, placement, CTS, routing, timing analysis, and signoff.
Role type
Physical Design Engineer Intern
Builds
Chip/Block floorplans and GDS layouts
Domain
Semiconductor / Physical Design
Required skills
Synthesis, DFT logic insertion, ATPG pattern generation, Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, Timing Analysis, Static Timing Analysis (STA), Signal Integrity (SI) analysis, IR-drop analysis, DRC/ERC/PERC/LVS checks, Primetime
Technologies
Verilog, Primetime
Responsibilities
Handle synthesis/DFT logic insertion and ATPG pattern generation; Handle physical design tasks from verilog netlist to GDS; Handle Chip/Block floorplan, PD implementation, include placement, CTS, PCTS, routing, timing analysis, SI analysis and IR-drop analysis; Timing fix and signoff with timing check tool Primetime; Finish DRC/ERC/PERC/LVS checks.
Seniority
Intern
