Staff/ Sr Staff Engineer, Physical Design
Core
Own RTL synthesis from elaboration to final sign-off, perform logic equivalence checks (LEC), develop and debug UPF, and manage power domains for complex SoC designs.
Role type
Staff/Sr Staff Physical Design Engineer (Backend)
Builds
Complex SoC designs for automotive, industrial, infrastructure, and IoT markets
Domain
Semiconductor backend design (Physical Design, Synthesis, Low-Power)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (SoC designs)
Required skills
RTL synthesis, LEC closure, UPF development, power domain modeling, TCL scripting, DFT insertion, low-power sign-off (VCLP)
Preferred skills
Advanced node experience (7nm/5nm), power-aware ECO, physical-aware synthesis, subsystem/SoC-level UPF ownership
Technologies
Cadence Genus, Synopsys Fusion Compiler, Conformal, VCLP, TCL
Responsibilities
Own RTL synthesis from elaboration to final sign-off; Develop and debug design constraints and support DFT insertion; Perform and close logic equivalence checks (LEC) across RTL, synthesized, and ECO netlists; Create, maintain, and debug UPF ensuring alignment with FE power intent; Define and manage power domains (power switches, isolation, retention, always-on); Support low-power sign-off (VCLP / power checks); Handle RTL ECOs during late design stages; Automate flows using TCL scripting
Seniority
Staff/Sr Staff, hands-on IC