Staff/Senior Staff Physical Design Floorplan & PDN Lead
Core
Architecting chip-level floorplans and Power Delivery Networks (PDN) for complex, large-scale SoCs to balance performance, power, and area.
Role type
Staff/Senior Staff Physical Design Floorplan & PDN Lead
Builds
Chip-top floorplans and PDN architectures for multi-million gate designs
Domain
Semiconductor Physical Design / Advanced Node IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Hierarchical physical design, Macro placement, Pin assignment, IR-drop analysis, Electromigration analysis, Tcl scripting, Python scripting, Perl scripting, Thermal-aware PDN design, Metal stack usage, Grid density optimization
Preferred skills
Experience with 7nm/5nm/3nm nodes, Cross-functional collaboration with RTL teams, Methodology development
Technologies
Innovus, IC Compiler II
Responsibilities
Lead chip-level floorplanning including macro placement and partition definition; Architect and implement complex Power Delivery Networks; Perform IR-drop and Electromigration analysis; Collaborate with RTL teams to optimize micro-architecture; Establish best practices and automated flows for floorplanning and PDN synthesis
Seniority
Senior Staff, hands-on IC design lead
