Front-End CAD Methodology Engineer – Design/DV Interface
Core
Design and manufacture next-generation, high-performance, power-efficient processor and system-on-chip (SoC) by creating robust, scalable methodology solutions for RTL Design and DV teams.
Role type
Senior IC Front-End CAD Methodology Engineer
Builds
Scalable, reusable methodology solutions and GenAI-enabled tooling for silicon development and verification
Domain
Semiconductor / Hardware Design / Verification
Deliverable
production ML models
Required skills
Front-End ASIC workflows, Artificial intelligence and machine learning, Static verification, Formal verification, Simulation, Emulation, Python, TCL, Perl, JSON, YAML, Verilog, SystemVerilog
Preferred skills
Debugging vendor tool problems, Cadence tools, Synopsys tools, VHDL, Large-scale software system development, MSEE/CE/CS degree
Technologies
GenAI, Python, TCL, Perl, JSON, YAML, Verilog, SystemVerilog, VHDL, Cadence, Synopsys
Responsibilities
Design and architect innovative solutions including GenAI-enabled tooling, drive adoption of methodology solutions across a globally distributed engineering organization, work with design and verification engineers to define requirements and implement solutions, create and maintain high quality flows for Apple Silicon production
Seniority
Senior, hands-on IC with technical leadership
