Static Timing Analysis Engineer
Core
Analyze and verify the timing of digital circuits to ensure they meet performance requirements under various operating conditions.
Role type
Senior Static Timing Analysis Engineer (Digital IC Design)
Builds
Digital circuit designs meeting timing closure for hyperscale and low technology nodes
Domain
Semiconductor / Digital IC Design / Low Technology Nodes
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Static Timing Analysis (STA), Digital circuit design principles, Timing analysis tools and methodologies, Complex timing issue analysis, Design verification processes
Preferred skills
Finfet low technology node expertise (7nm and below), IO budgeting, MMMC timing eco generation, Clock Tree analysis, AOCV/POCV margin methodology, Hyperscale/ILM experience, Team management, Mentoring
Technologies
PrimeTime, Tempus, Fishtail
Responsibilities
Full Chip level Constraints development, validation, and timing closure; Perform timing optimizations and resolve setup/hold violations; Collaborate with design and verification teams to refine timing models; Mentor junior team members; Evaluate and implement best practices in static timing analysis
Seniority
Senior, hands-on IC with team leadership
