Sr Engineer, Design Enablement
Core
Develop and define Synthesis & Static Timing Analysis (STA) flows and methodologies for Advanced SoCs and MCUs on low geometry nodes (3/5/16/22nm).
Role type
Senior IC Synthesis Engineer (Flow & Methodology)
Builds
Production digital logic flows and methodologies for SoCs/MCUs
Domain
Semiconductor / VLSI / Digital Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL design, Synthesis, LEC, VCLP, Timing Constraints, UPF, Timing Signoff, EDA tools (Genus, Fusion Compiler, Conformal, Tempus, Primetime), Scripting (PERL/TCL/Python)
Preferred skills
Experience with low geometry nodes, EDA vendor tool evaluation
Technologies
Genus, Fusion Compiler, Conformal, Tempus, Primetime, PERL, TCL, Python
Responsibilities
Define Synthesis & STA flow and methodology for Advanced SoCs & MCUs, Manage requirements for SoCs/MCUs designs, Evaluate and benchmark latest EDA tool offerings, Deploy new tools & methodologies across the organization
Seniority
Senior, hands-on IC
