SOC RTL Design Engineer
Core
IP/BLK level RTL integration and design of IP/glues/wrappers involving complex high-speed protocol integration.
Role type
RTL Design Engineer (System Architecture)
Builds
IP blocks, glue logic, and wrappers for System LSI, Memory, and Foundry solutions.
Domain
Semiconductor, High-Speed Serdes, System-on-Chip (SoC)
Deliverable
production ML models | product features | infrastructure
Required skills
Front-end RTL design and integration, High-Speed Serdes protocols (PCIe, USB, UFS, MIPI, DFI, AMBA), RTL verification tools (LINT, VCLP, CDC, RDC, SYNTHESIS, Meggalan), Design Constraints (SDC) handling, Scripting (Perl, Python, TCL)
Preferred skills
DFT insertion strategies, AFL/XPROP/DFT tool knowledge, Storage/Display/Memory domain expertise
Technologies
LINT, VCLP, CDC, RDC, SYNTHESIS, Meggalan, SDC, Perl, Python, TCL
Responsibilities
Perform IP/BLK level RTL integration and design, Handle cross-functional reviews for test plans, coverage, synthesis constraints, and DFT insertion strategies
Seniority
Mid-Senior, hands-on IC
