ASIC Physical Design
2,687 open positions
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High-Speed I/F Subsystem Design Leader Renesas-ElectronicsKodaira, jp 7mo Define design direction and make technical decisions for the High-Speed I/F subsystem of automotive SoCs (R-Car series), focusing on PCIe, UCIe, USB, and UFS.
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ASIC Engineering Lead CiscoArmenia 7mo Lead end-to-end physical implementation of high-complexity silicon blocks from RTL to tape-out, ensuring production-ready design delivery for innovative networking technology.
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Senior Director, SoC Power and Clocking Technology ArmMultiple locations $383k7mo Lead a global team to architect and deliver verified designs for SoC power, clocking, reset, and thermal management solutions.
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Senior Logic Design Engineer, CPU Core NVIDIAIsrael, Yokneam 7mo Design and own units within a CPU core micro-architecture, writing RTL and collaborating with verification and implementation teams to meet timing, area, performance, and power goals.
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Neural Processing Unit Digital Designer MediaTekHsinChu 7mo Designing, developing, and optimizing the architecture of neural processing units (NPUs) to meet performance, scalability, and efficiency requirements.
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Staff Digital Design Engineer ON SemiconductorCork, Co. Cork, Ireland 7mo Architecting and implementing digital FSM-based controllers and digital-on-top subsystems for mixed-signal and power management solutions.
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Lead STA Engineer Texas InstrumentsBengaluru, Karnataka, India 7mo Drive timing closure and synthesis optimization for advanced connectivity SoCs to ensure wireless solutions meet performance, power, and area requirements.
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Senior/Expert Hardware Design Engineer - FPGA Sopra-SteriaMontréal, QC, ca 7mo Design, develop, and validate complex electronic modules (FPGA, CPLD, electronic boards, ASIC) for automotive and avionics applications, focusing on video processing and 4K resolution pipelines.
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Power Optimization Engineer EtchedaiHardware Engineering 7mo Develop chip power models, estimate power from microarchitecture, and devise power-saving techniques for AI ASICs.
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STA Engineer (M, F, D) AppleMunich, Germany 7mo Developing automated block and full chip level signoff flows, ensuring full chip timing/noise convergence and high-quality timing signoff.
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Principal SoC RTL Engineer AmbiqmicroincAustin HQ 7mo Own pre-tapeout quality for digital SoC modules on MCU platforms and drive architecture, microarchitecture, and RTL development for next-generation silicon.
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FPGA / Embedded Design Entwickler/In Trenz Electronic GmbHHüllhorst, NORDRHEIN_WESTFALEN 7mo Development of customer-specific FPGA/SoC designs and system architecture for complex industrial applications.
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High‑Speed IP Integration Engineer, Up to Snr Staff (USB/PCIe/UHS) (Hsinchu, Taipei) QualcommHsinchu City, Taiwan 7mo Architecting and implementing RTL designs for complex SoC platforms, focusing on the integration and performance evaluation of 3rd party IPs like USB, PCIe, and UHS.
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Sr. Lead ASIC design Engineer - Digital Design NxpHyderabad 7mo Define and implement hardware architectures optimized for AI inference SoCs, including custom-ISA processors and high-speed interconnects.
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Senior Out-of-Order CPU Architect IntelUS, Texas, Austin $191k7mo Define end-to-end CPU architecture specifications and microarchitectures for high-performance and low-power computing products.
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Automotive Senior Hardware Engineer / Specialist / Architect Bosch-Groupcoimbatore, in 7mo Lead hardware design and development for vehicle computers, communication gateways, zone ECUs, and power distribution ECUs from concept to production.
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Lead Design Engineer CadenceBANGALORE 7mo Lead Design Engineer responsible for RTL coding, datapath designs, complex FIFO design, and high-speed SerDes IP development.
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Senior FPGA Design Engineer (f/m/div) InfineonLviv (Ukraine) 8mo Convert full-chip microcontroller ASIC to FPGA, define design constraints, and debug RTL integration.
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