IP RTL Design Engineer
Core
Senior IP Design Engineer developing RTL, synthesis, and verification for complex Image Sensor IP modules.
Role type
Senior IC RTL Design Engineer (Image Sensors)
Builds
Image Sensor IP modules for Samsung Image Sensors
Domain
Semiconductor / Image Processing / Hardware Design
Deliverable
production ML models | product features
Required skills
RTL coding (Verilog/System Verilog/VHDL), Synthesis (Synopsys DC, RTL-A), Timing analysis (SDC), Lint/CDC/DFT checks, Power optimization, Functional specification writing, ECO development
Preferred skills
RTL integration tools (Magillem), HLS tools (Stratus/Catapult)
Technologies
Verilog, System Verilog, VHDL, Synopsys DC, RTL-A, SDC, Xcellium, VCS, Verdi, Spyglass, Magillem, Stratus, Catapult
Responsibilities
Architecture and RTL development for Image Processing IP, Technically lead RTL modules development, Interface with cross-functional teams (Algorithm, Verification, Physical Implementation), Ensure design quality using Lint and CDC checks, Perform synthesis, area and power optimization
Seniority
Senior, hands-on IC
