CPU STA - Sr/Lead/Staff/Sr Staff Engineer
Core
Senior CPU Static Timing Analysis (STA) engineer responsible for timing closure, constraint management, and verification in high-speed ASIC designs.
Role type
Senior IC hardware engineer (CPU STA)
Builds
High-speed CPU micro-architectures with timing closure
Domain
Semiconductor / Hardware Engineering / CPU Design
Required skills
Static Timing Analysis (STA), Place & Route (FC/Innovus), ASIC flow optimization, UPF/CPF power domain implementation, Formal verification, Perl/Tcl/Python/C++, Verilog, Clock Tree Synthesis, Constraint generation and validation
Preferred skills
Low power implementation techniques, High speed CPU implementation experience
Technologies
Primetime, Tempus, Innovus, FC, Formality, Conformal, UPF, CPF, Perl, Tcl, Python, C++, Verilog
Responsibilities
Perform Static Timing Analysis (STA) using Primetime and/or Tempus; Generate and validate timing constraints; Implement complex power domains with UPF/CPF; Execute formal verification using Formality/Conformal; Optimize ASIC flow for low power, performance, and area; Implement clock trees for high-speed designs; Debug timing issues in CPU micro-architecture.
