Senior Physical Design Backend Engineer
Core
Design high-speed communication chips by performing physical design of blocks, resolving timing and congestion, and managing RTL-to-GDS flows to optimize power, area, and performance.
Role type
Senior Physical Design Backend Engineer
Builds
High-speed networking silicon chips
Domain
Semiconductor / Networking
Required skills
RTL2GDS flows, PNR, STA, physical verification (LVS/DRC), power and clock distribution, place and route, timing closure, physical design EDA tools
Preferred skills
High cell count design experience, HS blocks experience, flows development
Technologies
Synopsys, Cadence
Responsibilities
Perform physical design of blocks under challenging constraints; Resolve complex timing and congestion problems; Execute RTL2GDS flows including synthesis, place and route, and verification; Participate in flows development.
Seniority
Senior, hands-on IC
