CPU Design Verification Engineer II
Core
Verify high-performance out-of-order RISC-V CPU cores from RTL bring-up through tapeout, focusing on block and core-level validation including pipeline hazards, memory-ordering violations, and speculation corner cases.
Role type
Senior IC CPU Design Verification Engineer
Builds
RISC-V processor cores for AI, machine learning, automotive, data center, mobile, and consumer applications
Domain
Semiconductor / CPU Design / RISC-V Architecture
Required skills
SystemVerilog, UVM, Computer Architecture (pipelining, out-of-order execution, cache hierarchy), Simulator debugging (VCS/Questa/Xcelium), Waveform analysis (Verdi), C/Assembly programming, Python scripting, Git
Preferred skills
Out-of-order core verification, RISC-V extensions (V, H, A), ISA co-simulation (spike), Formal property verification, Memory-model verification, Emulation/FPGA prototyping
Technologies
UVM, SystemVerilog, VCS, Questa, Xcelium, Verdi, Spike, Python, Git, C, Assembly
Responsibilities
Own verification plans for OOO core units; Build and extend UVM testbench infrastructure; Develop constrained-random and directed tests; Debug regression failures end-to-end; Drive coverage closure; Maintain regression health; Contribute to verification tooling and CI integration
Seniority
Mid-level, hands-on IC
