Sr. ASIC Design Verification Engineer
Core
Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure for Cisco high-end switching products.
Role type
Senior IC ASIC Design Verification Engineer
Builds
ASIC verification environments and testbenches for high-end switching products
Domain
Networking hardware / ASIC design
Required skills
System Verilog, UVM, ASIC design verification, testbench construction (scoreboard, agents, sequencers, monitors), simulation models, test plans, code/functional coverage, multi-chip/system simulation, post-silicon debugging
Preferred skills
Ethernet protocols, high-speed SerDes interfaces, Linux, C/C++, Python/Perl, PCIe and AXI protocols, data center/hyperscaler/AI networking experience, large-scale SoC architectures
Technologies
System Verilog, UVM, Linux, C, C++, Python, Perl, PCIe, AXI
Responsibilities
Develop simulation models, test plans, direct and random tests, code or functional coverage, multi-chip/system simulation, and performance analysis; Construct testbenches components like scoreboard, agents, sequencers, and monitors; Collaborate with designers, architects, and software teams to debug issues during post-silicon bring-up and integration; Ensure comprehensive verification coverage through code and functional coverage implementation and review
Seniority
Senior, hands-on IC
