Digital Verification Engineer (all genders)
Core
Own verification strategy, testbench development, and sign-off readiness for assigned IPs, subsystems, or distributed systems.
Role type
Senior IC digital verification engineer
Builds
Reusable verification environments, testbenches, and infrastructure for digital ICs
Domain
Semiconductor / Digital IC Design
Required skills
SystemVerilog, UVM, constrained-random verification, assertion-based verification (SVA), coverage-driven verification, RTL development, digital design fundamentals, regression management, Python/Tcl scripting, SoC-level verification
Preferred skills
Mentorship, automation, tool optimization, new verification methodologies
Technologies
SystemVerilog, UVM, Python, Tcl, industry-standard simulators, debuggers, waveform analysis tools
Responsibilities
Own verification planning and scope definition, develop and maintain verification environments, execute coverage closure, debug design defects, manage regression suites, support sign-off reviews, mentor junior engineers
Seniority
Senior, hands-on IC
