DFT Engineering Director, CPU Cores Design for Testability
Core
Senior technical leader driving Design for Testability (DFT) execution and roadmap for future AMD CPU cores from concept to production.
Role type
Senior IC DFT Engineering Director
Builds
High-performance CPU cores with embedded DFT features
Domain
Semiconductor / CPU Design
Required skills
DFT architecture, JTAG, ATPG, Scan, MBIST, LBIST, ATE debug, IP-level verification, Verilog/System Verilog, leadership, workforce planning
Preferred skills
x86 architecture, System C/C++, ICL/PDL, scripting, AI integration
Technologies
JTAG, ATPG, Scan, MBIST, LBIST, ATE, Verilog, System Verilog, System C, C++, ICL, PDL
Responsibilities
Functional management of DFT organization, develop future DFT features, drive DFT across CPU roadmap generations, establish execution frameworks, foster culture of innovation, drive workforce and succession planning
Seniority
Director, executive leadership & technical strategy
