Senior Manager Verification
Core
Leading full-chip verification strategy, coverage closure, and DV execution for complex ASIC/SoCs from planning through tape-out and silicon bring-up.
Role type
Senior Manager, ASIC/SoC Verification
Builds
Production-ready silicon chips
Domain
Semiconductor / Hardware Design
Required skills
System Verilog, UVM, Formal verification, Mixed-signal verification, Register/RAL verification, Multi-clock/CDC verification, Reference-model-based verification, Coverage closure, Regression infrastructure, Cross-functional leadership
Preferred skills
Experience with safety, DFT, and physical design teams
Technologies
System Verilog, UVM, C, MATLAB, DPI
Responsibilities
Own full-chip verification strategy and sign-off criteria; Drive coverage closure and regression infrastructure; Represent verification in cross-functional forums; Manage verification schedule, resources, and risks; Drive methodology and reuse across subsystems.
Seniority
Senior Manager, hands-on IC
