Senior Digital ASIC Verification Engineer
Core
Senior Digital ASIC Verification Engineer responsible for verifying complex, highly integrated digital ASICs, focusing on top-level functionality, cross-IP interactions, and system-level use cases.
Role type
Senior IC digital ASIC verification engineer
Builds
Complex digital ASICs and SoCs for high-speed connectivity networking infrastructure
Domain
Semiconductor / Networking
Required skills
SystemVerilog, UVM, formal verification, verification planning, coverage analysis, cross-IP integration, debugging, technical mentoring
Preferred skills
SystemVerilog Assertions (SVA), Python scripting, Bash, Make, high-speed networking (Ethernet/OTN)
Technologies
SystemVerilog, UVM, Python, Bash, Make
Responsibilities
Develop and maintain SystemVerilog/UVM functional verification environments, testbenches, testcases, checkers, and assertions; Develop cross-IP and system-level test scenarios; Translate architecture and design specifications into comprehensive verification plans; Integrate block-level verification components into subsystem and top-level environments; Mentor junior engineers
Seniority
Senior, hands-on IC
