Design Verification Engineer II
Core
Design Verification Engineer responsible for creating constrained-random verification environments, formal verification, and debugging complex CPU or SoC IP designs to ensure functional correctness before tape-out.
Role type
Senior IC design verification engineer (SoC/CPU)
Builds
Custom IP and System-on-Chip (SoC) designs
Domain
Semiconductor / Computer Architecture
Required skills
SystemVerilog, UVM, C++, Python, Perl, RTL debugging, formal verification (SVA), functional coverage, computer architecture knowledge
Preferred skills
Debugging simulation/emulation environments, complex CPU/SoC IP delivery track record
Technologies
SystemVerilog, UVM, SVA, Python, Perl, Verilog
Responsibilities
Plan verification strategies for complex design IP/SoC, create and enhance constrained-random verification environments, develop tests using UVM or C/C++, analyze and debug test failures, identify and write functional coverage for stimulus and corner cases, close coverage to meet tape-out requirements
Seniority
Mid-Senior, hands-on IC
