IP Manager, Design and Verification - Networking
Core
Lead and manage a cluster of IP teams responsible for design and verification of complex hardware IP blocks for NVIDIA's SmartNIC and DPU products.
Role type
Senior IC IP Manager (Design & Verification)
Builds
SmartNIC and DPU hardware IP blocks
Domain
Semiconductor / Networking
Required skills
Digital design fundamentals, RTL coding (Verilog/SystemVerilog), Verification methodologies (UVM, e-specman), Formal verification, EDA tools, Team leadership, Project management
Preferred skills
High-speed interfaces (PCIe, NVLink, HBM, DDR, SerDes), Verification infrastructure (CI/CD, emulation), Scripting (Python, Perl, TCL), GPU/AI/HPC domain experience
Responsibilities
Lead and mentor design and verification engineers, Own end-to-end IP delivery lifecycle, Define verification strategies and sign-off criteria, Partner with cross-functional teams (architecture, SoC, physical design), Establish design and verification methodologies
Seniority
Senior, hands-on IC with management responsibilities
