Wireless Design Verification Engineer
Core
Verify Radio digital controllers and RF subsystems for WiFi SoCs to ensure first-time-right silicon success.
Role type
Senior IC verification engineer (digital/mixed-signal)
Builds
Verification environments, testbenches, and scenarios for complex radio control and datapath subsystems
Domain
Semiconductor / Wireless Connectivity / SoC Design
Required skills
SystemVerilog, UVM, RTL simulation, Python, digital design fundamentals (Verilog/VHDL), constrained random testing, functional coverage, mixed-signal modeling
Preferred skills
RF/analog system design (PLLs, DAC/ADCs, LNAs, Mixers), assertion-based verification, Perl/Bash scripting
Technologies
SystemVerilog, UVM, Python, Verilog, VHDL, DMS models
Responsibilities
Develop UVM testbench environments and bus functional models; Implement constrained random scenarios for radio protocols and state machines; Collaborate on digital + mixed-signal verification using analog behavioral models; Drive closure by tracking regressions and addressing coverage gaps; Partner with cross-functional teams to define verification strategy; Develop Python automation for verification flows.
Seniority
Senior, hands-on IC
