FY27 Intern - Design Verification Engineering Internship - Canada (16 months)
Core
End-to-end verification of DSP-based SoC chips for high-speed connectivity products.
Role type
Design Verification Engineering Intern
Builds
DSP/SoC features for high-speed connectivity products
Domain
Semiconductors, Digital Hardware, Connectivity
Required skills
SystemVerilog, UVM, Python, C/C++, Shell scripting, Simulation tools (Synopsys VCS/Verdi), Debugging, Coverage analysis, DSP architecture knowledge, SoC subsystems knowledge
Preferred skills
Electrical/Computer Engineering background, Detail-oriented task planning
Technologies
SystemVerilog, UVM, Synopsys VCS, Synopsys Verdi, Python, C/C++, Shell
Responsibilities
Develop SystemVerilog/UVM testbenches, tests, assertions, checkers, and coverage; Run simulations and debug complex failures using industry-standard tools; Verify feature interactions across DSP blocks, digital logic, interfaces, firmware, and other SoC subsystems; Develop scripts and automation to improve verification productivity; Explore and apply AI/ML technologies to improve verification workflows; Support post-silicon validation and lab activities.
Seniority
Intern
