ASIC RTL Design Verification Manager
Core
Lead pre-silicon functional verification organization for ASIC/SoC programs, owning strategy, methodology, execution, and sign-off to deliver high-quality RTL and predictable tape-out schedules.
Role type
Senior Manager, ASIC RTL Design Verification
Builds
High-performance semiconductor processors (SoC) for AI, healthcare, and consumer applications
Domain
Semiconductor / ASIC Design / Digital Logic
Deliverable
production ML models
Required skills
C/C++, ASM, SystemVerilog, UVM, digital RTL architecture, SoC architecture, verification strategy, team leadership, coverage-based verification, clock/reset architectures, memory interfaces, power management
Preferred skills
Multi-core SoC verification, high-speed protocols (PCIe, CXL, Ethernet, DDR), X86/ARM subsystems, GFX/GPU SoC, reusable UVM IP, low-power verification (UPF), Python scripting
Technologies
SystemVerilog, UVM, Python, UPF, PCIe, CXL, Ethernet, DDR, X86, ARM
Responsibilities
Define verification strategy and sign-off criteria; drive full-chip verification planning and execution; guide development of scalable testbench architectures; lead verification execution across multiple projects; build and mentor high-performing verification teams; collaborate with RTL design, architecture, and program management teams
Seniority
Senior, hands-on IC with significant people leadership
