Senior DFT engineer
Core
Design-for-Test (DFT) engineer implementing and verifying DFT solutions for complex hierarchical SoC/ASIC designs to ensure first-pass silicon success.
Role type
Senior IC DFT engineer
Builds
DFT architectures, test strategies, and verification environments for SoC/ASIC chips
Domain
Semiconductor / SoC/ASIC Design
Required skills
DFT architecture design, scan insertion, test compression (SSN), Boundary Scan (IEEE 1149.x), ATPG generation, gate-level simulation, TCL/Perl/Python scripting, ATE flow knowledge
Preferred skills
5+ years DFT experience, Siemens Tessent tool expertise, Advantest/Teradyne platform familiarity
Technologies
Siemens Tessent, Verilog, Gate-level simulators, STIL/WGL formats
Responsibilities
Develop DFT architectures for hierarchical SoC/ASIC designs; Perform scan and test point insertion; Validate SSN topology and manage clock domain crossings; Integrate Boundary scan and test access mechanisms; Generate and analyze ATPG patterns; Perform DFT verification via simulation; Collaborate with ATE teams on pattern files; Support silicon bring-up and failure analysis
