R&D Engineer IC Design
Core
Design for Test (DFT) engineer responsible for SoC DFT activities including architecture, test insertion, verification, pattern generation, coverage improvement, and post-silicon debug to meet product test metrics.
Role type
Senior IC DFT Engineer
Builds
SoC designs with integrated DFT for ASIC Product Division
Domain
Semiconductor / ASIC Design
Required skills
DFT concepts, ATPG, MBIST, JTAG, DFT insertion & verification, pattern generation, coverage improvement, vector simulation, post-silicon debug, scripting (Perl, Shell), timing closure collaboration
Preferred skills
Mentor Graphics DFT tools (TestKompress, Fastscan), cross-geography team collaboration
Responsibilities
Work on DFT architecture, test insertion and verification, pattern generation, coverage improvement, post silicon debug and yield improvement, collaborate with Physical Design & STA team for DFT mode timing closure, interact with external customers
Seniority
Senior, hands-on IC with supervision responsibilities
