Design Verification Senior Manager
Core
Leading the Design Verification organization for analog mixed signal portfolio (SerDes, DDR, PLLs, data converters) with a focus on AI-driven verification methods.
Role type
Senior Manager, Design Verification
Builds
Verification strategy, organizational structure, and AI-enabled verification practices for analog mixed signal IP
Domain
Semiconductor / Analog Mixed Signal / Design Verification
Deliverable
production ML models
Required skills
Analog mixed signal verification, UVM methodology, organizational leadership, strategic planning, risk management, hiring and retention, cross-functional partnership, technical trade-off analysis
Preferred skills
AI in verification workflows, executive communication, multi-site team management, advanced degree (MS/PhD)
Technologies
UVM, AI/ML for verification
Responsibilities
Structure teams and assign responsibilities, set verification strategy and standards, track results and risks, communicate status to upper management, partner with design and firmware teams, manage hiring and retention, mentor leads
Seniority
Senior, hands-on IC with management