Design Verification Engineer Intern (Summer 2027)
Core
Verify CPU core functionality, performance, and modeling using advanced verification methodologies.
Role type
Design Verification Engineer Intern
Builds
CPU verification environments and testbenches
Domain
Semiconductor / CPU Design
Required skills
SystemVerilog, UVM, constrained-random verification, Python scripting, cache/coherency concepts, CPU architecture knowledge (RISC-V, ARM, MIPS)
Preferred skills
FPGA prototyping, interconnect protocols (AXI, ACE, CHI), AI tools for productivity
Technologies
SystemVerilog, UVM, Python, Perl, Shell, C, Assembly
Responsibilities
Develop and execute verification plans including testbench creation; Write directed and constrained-random test cases; Analyze coverage reports to close gaps; Automate regression flows; Collaborate with architects on design quality.
Seniority
Intern
